A Novel Multiple Buses Controller in Multiprocessors

Abstract

A configurable dual-core embedded system for multimedia application of System-on-Chip (SoC) was introduced in this paper, in which we described a SoC consisting of a master processor and a slave processor. The master processor is represented by the simulator of SimpleScalar. In addition, the slave processor collocates with Xtensa processor, which is able to establish excellent multimedia application than the traditional designs. They get benefit in area and power characteristics. This proposed architecture can be configured in multiprocessors architecture, and verified by a provided simulation program. The main functional blocks integrated in this system includes dual cores, local memory, cache memory, shared memory, shared bus, and so forth.