RF-DSP: A Reconfigurable and Highly Flexible FPGA-based Digital Signal Processor

Abstract

Digital Signal Processor (DSP) is becoming an increasingly important chip in the digital electronic world, showcasing its capabilities in fields such as video processing, mobile communications, radar systems, and more. Application Specific Integrated Circuit (ASIC) and Programmable Digital Signal Processors (PDSP) continue to be commonly used implementation mechanisms for many digital signal processing applications. However, both of these platforms have their limitations. The non-reconfigurable arithmetic units of ASIC circuits compromise flexibility, making it difficult to support new algorithms. The performance of DSP chips is limited by a serial instruction stream, making it challenging to break through performance bottlenecks. To address these challenges, we have proposed RFDSP, a reconfigurable and highly flexible digital signal processor based on Field Programmable Gate Arrays (FPGA), aimed at accelerating digital signal processing algorithms. We have customized an instruction set that enables RF-DSP to support various digital signal processing algorithms. RF-DSP features multiple parallel arithmetic units that can be reused to support different algorithms. Additionally, RFDSP exhibits excellent scalability, allowing for the incorporation of dedicated components and enhancements to the instruction set to support continuously evolving digital signal processing algorithms. We have implemented a hardware prototype on Xilinx Alveo U200 and conducted performance testing on RFDSP. Compared to DSP chips, RF-DSP achieves acceleration of 1.3-136 times and improves efficiency by 4-400 times. Compared to Xilinx IP, it achieves acceleration of 7-16 times and improves efficiency by 6-14 times.