Efficient Searching with a TCAM-based Parallel Architecture

Abstract

Ternary Content-Addressable Memory (TCAM) is a popular hardware device for fast IP address lookup. High link transmission speed of Internet backbone demands more powerful IP address lookup engine. Restricted by the memory access speed, the lookup engine for next-generation routers demands exploiting parallelism among multiple TCAM chips. How to design an efficient engine with high IP lookup speed and less update time while keeping low power consumption is a great challenge in building the next-generation routers. At present, no parallel schemes can make full use of TCAM chips’ capability. In this paper, we propose a fast lookup, efficient update and power-saving scheme which can basically make full use of TCAM chips’ capability. With N parallel TCAM chips, our proposed scheme can achieve a worst-case speedup factor of (N-1)*90% in cache-update state, and a worst-case speedup factor of N*90% in normal work state. Compared with previous works, our scheme can apparently improve IP lookup performance and update efficiency while keeps low power consumption.