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Dynamic Parallel Computing Architecture for Video Processing

K. Bharanitharan,
Anand Paul,
Yung-Chuan Jiang,
Jhing-Fa Wang,

Abstract


In this paper, motion estimation preprocessing algorithm is mapped onto a new dynamically parallel computing architecture, namely, the parallel computing architecture, which consists of multiple parallel units. It eventually reduces the computation required for motion estimation in advance video coding. A directed acyclic graph is constructed to represent the video coding algorithms comprising motion estimation. This speeds up the video processing with minimum sacrifice.

Keywords


Motion estimation; Video coding; Parallel processing; Parallel architecture; FPGA

Citation Format:
K. Bharanitharan, Anand Paul, Yung-Chuan Jiang, Jhing-Fa Wang, "Dynamic Parallel Computing Architecture for Video Processing," Journal of Internet Technology, vol. 11, no. 6 , pp. 867-873, Nov. 2010.

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Published by Executive Committee, Taiwan Academic Network, Ministry of Education, Taipei, Taiwan, R.O.C
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