A High-Performance Programmable Scheduling Engine for ATM Switches

Abstract

ATM networks provide high-throughput low-latency communication for various types of applications, such as voice, video, and multimedia. ATM switches with quality service are the key components in these networks. In this paper, the VLSI design and implementation of a scheduling engine for ATM switches are presented. This scheduling engine can efficiently arbitrate cells from input output ports in the ATM switch. The scheduling engine efficiently compares the information of cells and determines which cell can be sent to the output port. An important feature of the engine is programmability. Using some programmable options implemented in the hardware, the scheduling engine is flexible enough to perform different scheduling schemes. With the proposed architecture, ATM switches can satisfy several scheduling requirements and achieve high throughput. Our design has been implemented in a VLSI chip to validate the idea.