An Approach to Reduce Soft Error Rate of SRAM-Based FPGA with SEU Effects by Partial Mitigation and PSO

Abstract

Soft Error is a big challenge for FPGA-based digital systems' reliability and life in radiation environments. In this paper, we present an approach to for reducing soft error rate (SER) in SRAM-based FPGA. The entire VHDL is divided into multiple modules according to function. The SER of each module is calculated by an analytic estimation method. And then we introduce the r/KPSO to determine the mitigation strategy rather than performing mitigation for all the modules. Only parts of whole modules are implemented with redundance mitigation which is determined by r/KPSO with maximum redundant area constrains. Experimental results showed that the proposed approach can provide one order of magnitude of SER reduction with about 70% redundant area cost.